90909 sy / 41509 ms 20090401-s00011 no.a1443-1/6 http://onsemi.com semiconductor components industries, llc, 2013 august, 2013 LV5761V overview the LV5761V is a 1-channel step-down switching regulator. functions ? 1 channel step-down switching regulator controller. ? frequency decrease function at pendent. ? load-independent soft start circuit. ? on/off function. ? built-in pulse-by-pulse ocp circuit. it is detect ed by using on resistance of an external mos. ? synchronous rectification. ? current mode control. ? synchronous drive by external signal. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v in max 45 v allowable power dissipation pd max mounted on a specified board. * 0.74 w operating temperature topr -40 to +85 c storage temperature tstg -55 to +150 c * specified board: 114.3mm 76.1mm 1.6mm, glass epoxy board recommended operating range at ta = 25 c parameter symbol conditions ratings unit supply voltage range v in 8.5 to 42 v error amplifier input voltage 0 to 1.6 v bi-cmos lsi 1-channel step-down switching regulator orderin g numbe r : ena1443a stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV5761V no.a1443-2/6 electrical characteristics at ta = 25 c, v in = 12v ratings parameter symbol conditions min typ max unit reference voltage block internal reference voltage vref incl uding offset of e/a 0.654 0.67 0.686 v 5v power supply v dd i out = 0 to 5ma 4.7 5.2 5.7 v triangular waveform oscillator block oscillation frequency f osc rt = 220k 110 125 140 khz frequency variation f osc dv v in = 8 to 42v 1 % oscillation frequency fold back detection voltage v osc fb fb voltage detection after ss ends 0.1 v oscillatory frequency after fold back f osc fb 1/3f osc khz on/off circuit block ic start-up voltage v en on 2.5 3.0 3.5 v ic off voltage v en off 1.0 1.2 1.4 v soft start circuit block soft start source current i ss sc en > 3.5v 4 5 6 a soft start sink current i ss sk en < 1v, v dd = 5v 2 ma uvlo circuit block uvlo lock release voltage v uvlo 7.5 8.0 8.5 v uvlo hysteresis v uvlo h 0.7 v ocp circuit block ocp charge current i ocp 5 a error amplifier input bias current i ea in 100 na error amplifier transconductance g ea 1000 1400 1800 a/v sink output current i ea osk fb = 1.0v -100 a source output current i ea osc fb = 0v 100 a current detection amplifier gain gisns 1.5 over current limiter circuit block reference current 1 i lim 1 mode = l (gnd) -10% 18.5 +10% a reference current 2 i lim 2 mode = h (v in ) -10% 37.0 +10% a over current detection comparator offset voltage v lim ofs -5 +5 ma over current detection comparator common mode input range v in -0.45 v in v pwm comparator vt max duty cycle = dmax 0.9 1.0 1.1 v input threshold voltage (fosc = 125khz) vt0 duty cycle = 0% 0.4 0.5 0.6 v maximum on duty dmax 80 85 90 % output block output stage on resistance (the upper side) r onh 5 output stage on resistance (the under side) r onl 5 output stage on current (the upper side) i onh 240 ma output stage on current (the under side) i onl 240 ma the whole device standby current i ccs en < 1v 10 a mean consumption current i cca en > 3v 3 ma
LV5761V no.a1443-3/6 package dimensions unit : mm (typ) 3178b pin assignment 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 fb comp en rt sync sw cboot hdrv ss ilim v in ocp mode gnd v dd ldrv LV5761V top view sanyo : ssop16(225mil) 5.2 4.4 6.4 0.22 0.65 (0.33) 18 9 16 0.5 0.15 1.5max 0.1 (1.3) -40 0 20 40 60 80 100 0 1.0 0.8 0.6 0.4 0.2 pd max -- ta -20 85 0.74 0.38 ambient temperature, ta -- c allowable power dissipation, pd amx -- w specified board: 114.3 76.1 1.6mm 3 glass epoxy board.
LV5761V no.a1443-4/6 block diagram rt sync 5 4 en 3 14 + - 5v regulator 12 v in mode 13 5 a 1.25v ocp comp1 + - ocp comp2 reference voltage osp logic + - v cc current amp s r q saw wave oscillator ocp 15 mode l 20 a mode h 40 a 5 a s r q + - sd 1.1v + - + sd 0.67v 16 1 2 + - 0.1v ss fb comp ilim ffold comp fosc forced 1/3 dmax = 90% 1.0v 0.5v + - control logic uvlo 8 9 10 11 6 7 cboot hdrv sw v dd ldrv gnd shut down(sd) 5v pwm comp pin function pin no. pin name description 14 v in power supply pin. this pin is monitored by uvlo function. when the voltage of this pin becomes 8v or more by uvlo function, the ic starts and the soft start function operates. 11 gnd ground pin. each reference voltage is based on the voltage of the ground pin. 10 v dd power supply pin for an external the lower mos-fet gate drive. 7 cboot bootstrap capacity connection pin. this pin become s a gate drive power supply of an external nchmosfet. connect a bypath capacitor between cboot and sw. 6 sw pin to connect with switching node. the source of nchmosfet connects to this pin. 5 sync external synchronous signal input pin. 9 ldrv an external the lower mosfet gate drive pin. 8 hdrv an external the upper mosfet gate drive pin. 1 fb error amplifier reverse input pin. by operating t he converter, the voltage of this pin becomes 0.67v. the voltage in which the output voltage is divided by an external resistance is applied to this pin. moreover, when this pin voltage becomes 0.1v or less after a soft star t ends, the oscillatory frequency becomes 1/3. 2 comp error amplifier output pin. connect a p hase compensation circuit between this pin and gnd. 16 ss pin to connect a capacitor for soft start. a capacitor for soft start is charged by using the voltage of about 5 a. this pin ends the soft start period by using the voltage of about 1.1v and the frequency fold ba ck function becomes active. 15 ilim reference current pi n for current detection. the sink current of about 20 a flows to this pin when low level (gnd) is set to the mode pin. also, the sink current of about 40 a flows to this pin when high level (v in ) is set to the mode pin. when a resistance is connected between this pin and v in outside and the voltage applied to the sw pin is lower than the voltage of the terminal side of the resistance, the upper nchm osfet is off by operating the current limiter comparator. this operation is reset with respect to each pwm pulse. 3 en on/off pin. 13 ocp pin to set the time of the timer (d uring double the over current detection point) connect a capacitor between this pin and gnd. ocp charge current : 5 a 4 rt pin to set the oscillation frequency. c onnect a resistance between this pin and gnd. 12 mode pin to switch the over current detection point. set by the low level (gnd) of the ilim pin. set by the high level (v in ) of the ocp pin. when this mode pin is set to the high level and the point of th e over current detection is set by using the ilim pin is exceede d, the value becomes double the original value. also, when the mode pin is set to the low level, the point of the over current detection remains an original value.
LV5761V no.a1443-5/6 timing chart when the mode pin is set to the high level and the point of the over current detection is set by using the ilim pin is exceeded, the value becomes do uble the original value. also, when the mode pin is set to the low level, the point of over current detection remains an original value. timing chart of the over current detection point switching is as below. t 1.25v current limit 2 a for example 6a current limit 1 a for example 3a over current detection point during high mode over current detection point during low mode load current 0v ocp mode = high sample application circuit sync c10 c4 q1 q2 l mode en ss comp rt cboot c1 c9 c7 c2 c8 c5 c3 sync h/l on/off v in = 8 to 42v out c6 c11 r5 r3 r2 r4 r7 hdrv sw ldrv fb v dd gnd ocp v in ilim 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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